Multiplexer Restructuring Statistics Report

This report appears in the Multiplexer Statistics folder.

Reports information about the Restructure Multiplexers logic option, which is an optimization technique for reducing the number of logic elements required to implement multiplexers.

Multiplexer Restructuring applies to entire hierarchical trees of multiplexers. Multiplexers may appear in different parts of the design through VHDL or Verilog HDL constructs, such as <if>, <case>, or <?>.

When multiplexers from one part of the design feed multiplexers in another part of the design, hierarchical trees of multiplexers are formed. Multiplexer Restructuring identifies buses of multiplexer trees that have a similar structure. Multiplexer buses occur most often as a result of combining vectors in Verilog, or STD_LOGIC_VECTORS in VHDL. When turned on, the Restructure Multiplexers logic option optimizes the structure of each multiplexer bus, taking advantage of the features in the target device so as to reduce the overall number of Logic Elements used. Area reductions as high as 20% are possible.

Multiplexer Restructuring is controlled from the Analysis & Synthesis Settings page. The default setting is auto, which means that Multiplexer Restructuring only takes place if the Optimization Technique is set to area or balanced. No restructuring takes place if the Optimization Technique is set to speed because in some cases, the clock speed of the design may be negatively affected.

Information for each bus of multiplexers is provided in the Multiplexer Restructuring Statistics report as follows:

• Multiplexer Inputs shows the number of data inputs to the multiplexer. For example, you would see 10:1 for a 10-to-1 multiplexer.
• Bus Width shows the width, in bits, of the bus.
• Baseline Size shows an estimate of how many logic elements are needed to implement the bus of multiplexers being described by the table row before any Multiplexer Restructuring takes place. This estimate can be used to highlight any large multiplexers in the design.
• Size if Restructured shows an estimate of how many logic elements are needed to implement the bus of multiplexers, if Multiplexer Restructuring is applied.
• Saving if Restructured shows an estimate of how many logic elements are saved if Multiplexer Restructuring is applied.
• Registered shows whether registers are present on the multiplexer outputs. Multiplexer Restructuring makes use of the additional features of a register (such as synchronous clear and synchronous load signals) to further reduce the number of logic elements needed to implement the bus of multiplexers.
• Example Multiplexer Output shows the name of one of the outputs of the multiplexers in the bus. This name can help determine from which part of the design the multiplexer bus originated.