User-Specified and Inferred Latches Report

This report appears in the Register Statistics folder.

Reports latches generated in a design, the latch name, latch enable signal, whether or not the latch presents a timing hazard, and the total number of user-specified and inferred latches.

A latch may be generated in a design for the following reasons:

• A latch is explicitly implemented using the appropriate primitive or the lpm_latch Intel^® FPGA IP:

  module my_latch(in, enable, clr, out);
  input in; 
  input enable, clr; 
  output out; 
  reg out; 
  always@(in or enable or clr); 
  begin if (clr) out = 1'b0; 
  else if (enable) out = in;  // When "enable" is true, "out" is assigned the value of "in" 
                              // when "enable" is false, "out" retains its previous value! This is a latch. 
  end;
  endmodule;

• A latch is inferred in HDL source code as in this example where a latch is inferred as a result of incompletely specified code:

  module my_latch3(data_a, data_b, data_c, select, clr, out);
  input data_a, data_b, data_c; 
  input [1:0] select; input clr; 
  output out; 
  reg out; 
  always@(data_a or data_b or data_c or select or clr) 
  begin if (clr) out = 1'b0; 
  else case (select) 2'b00 : out = data_a; 2'b01 : out = data_b; 2'b10 : out = data_c;  // out is not assigned when select = 2'b11 
                                                                                        // out retains its previous value! This is a latch. 
  endcase; 
  end; 
  endmodule;

Intel recommends that you only use latches when explicitly required in the design, and not as a result of incompletely specified HDL. Intel also recommends replacing latches, when possible, with registers. Register timing can be analyzed more accurately, and registers are not susceptible to glitches and can be simulated more easily than latches.

A design may also contain combinational loops that are not recognized by the Quartus^® Prime software as latches. These loops are not listed in the User-Specified and Inferred Latches report, but are reported in the Logic Cells Representing Combinational Loops report in the Synthesis Optimization Results folder.