Layers Details

Allows you to specify the graphic elements displayed for a given layer preset.

When you turn on or off the display of graphic elements, the settings apply to both the Chip Planner view and the Bird's Eye View. When you turn off graphic elements you can increase window refresh speed and reduce visual clutter when viewing complex designs.

You can choose whether to display the following graphic elements:

  • Background— The background color indicating the relative level of resource usage for different areas of the device.
    • None— No background color map.
    • Block Utilization— Indicates relative block usage.
  • Logic Lock Regions— Displays Logic Lock regions.
    • Assignments Logic Lock Regions— User-assigned Logic Lock regions.
    • Compilation Logic Lock Regions— Fitter-placed Logic Lock regions.
  • Clock Regions— The regional clocks to be displayed in the Chip Planner.
    • Global Clock Region— Displays only global clock regions.
    • Regional Clock Region— Displays only regional (quadrant) clock regions.
    • Large Periphery Clock Region— Displays only large periphery clock regions.
    • Small Periphery Clock Region— Displays only small periphery clock regions.
    • Spine Clock Region— Displays only spine clock regions.
    • Clock Sector Region— Displays sector boundaries clocks in designs targetting Stratix® 10 devices.
    • Design Clocks— Displays the size of each global signal in designs targetting Stratix® 10 devices.
  • Overlay Objects— Additional objects to be displayed.
    • Connection Lines—Connections resulting from any of the Chip Planner's Generate commands.
    • Labels—Labels on displayed connections resulting from any of the Chip Planner's Generate commands.
    • Differential Pin Pairs—Differential pin pairs. The function of this control is similar to the Show Differential Pin Pair Connections command.
    • Report Overlay—Graphic elements resulting from any of the Chip Planner's generated reports.
  • Routing Details— Routing information.
    • Local Routing— Logic routing within blocks.
    • Global Routing— Logic routing between blocks.
  • Logic Details— Logic information.
    • Logic Details— Detailed display of logic features.
    • Ports— Ports.
  • Node Coloring— Coloring scheme for node display.
    • None— No node coloring.
    • Utilization Level Based— Nodes are colored according to their level of utilization.
  • Other—Other objects to be displayed.
    • Unused Resources— Unused resources.
    • Pin and Location Assignments— Pin assignments and location assignments.