Logic Cells Representing Combinational Loops Report

This report appears in the Register Statistics folder.

Reports combinational loops encountered by Quartus^® Prime Synthesis and represents each loop as a logic cell Definition.

The following is an example of Verilog HDL source code where a combinational loop is detected:

 module top (ina, inb, out); 
input ina, inb; 
output out; 
assign out = (out & ina) | inb; 
endmodule

A combinational loop exists since the output pin out feeds itself through other combinational logic.

Combinational loops can lead to various problems in the design, including glitches and unstable or incorrect results. Combination loops can also make timing analysis cause glitches, unstable or incorrect results, make timing analysis difficult, and generally affect the stability and reliability of the design.

The Quartus^® Prime software might recognize some combinational loops as latches. Combinational loops recognized as latches are not listed in the Logic Cells Representing Combinational Loops report; they are listed in the Synthesis Optimization Results folder.