New or Edit

Allows you to specify the following settings for test bench files used by EDA third party simulation tools:

Test bench name— Requires you to specify the name of the test bench.

Scripting Information

Keyword: eda_test_bench_name

Settings: <string>

Test bench entity— Requires you to specify the entity name of the test bench. This name can be different from the test bench name.

Scripting Information

Keyword: eda_test_bench_module_name

Settings: <string>

Instance— Requires you to specify the instance name of the design in the test bench files.

Scripting Information

Keyword: eda_design_instance_name

Settings: <string>

Run for— (Optional) Allows you to specify the duration of the test bench simulation.

Scripting Information

Keyword: eda_test_bench_run_sim_for

Settings: <time>

Test bench files— Requires you to specify the test bench file Definition included in the test bench.
- To select the files to include, type or browse to the project directory.
- Test bench files can be Verilog Design File (.v) Definition, VHDL Design File (.vhd) Definition, Verilog Test Bench File (.vt) Definition, or VHDL Test Bench File (.vht) Definition.
- You must compile the files in order, so that files with dependencies go after the files they rely on.
- To adjust the file order, use the Up and Down buttons.

Note: Note: Verilog Test Bench Files and VHDL Test Bench Files are essentially Verilog Design Files and VHDL Design Files, respectively. The different extensions indicate that they are test bench files.

Scripting Information

Keyword: eda_test_bench_file

Settings: <file name>