Seed Sweep Only |
Directs
DSE II to vary only the seed setting in the
Fitter, using the seed values you specified in
Seeds.
The Fitter uses the seed during the
initial placement configuration and when optimizing
the design to meet the timing requirements,
including fMAX. Because each different seed value
will result in a somewhat different fit, you can try
different seeds to attempt to obtain superior
fitting results. Note: The seeds that lead to the best
fits for a design may change if the design
changes. Also, changing the seed not always
results in a better fit; therefore, you should
specify a seed only if the Fitter is not meeting
timing requirements by a small
amount
. |
All Compilation Strategies |
Optimizes synthesis for
balanced implementation that respects timing
constraints. When you specify this option, te number
of runs is 5x the number of seeds (+ optional base
compile). |
High Performance Effort |
The Compiler increases the
timing optimization effort during placement and
routing, and enables timing-related Physical
Synthesis optimizations (per register optimization
settings). Each additional optimization can increase
compilation time. |
Superior Performance with Maximum Placement
Effort |
Enables the same Compiler
optimizations as Superior Performance, with additional
placement optimization effort. |
High Performance
with Optimized Placement
Effort |
Optimize synthesis for speed performance, ,
with additional placement optimization
effort. |
Superior Performance with High Placement
Effort |
Optimize synthesis for speed
performance, with additional placement optimization
effort. |
Superior
Performance with Optimized Placement
Effort |
Optimize synthesis for speed performance.
Aggressive effort increases Fitter runtime and
device resource use. |
Superior Performance |
Enables the same Compiler
optimizations as High
Performance Effort, and adds more
optimizations during Analysis & Synthesis to
maximize design performance with a potential
increase to logic area. If design utilization is
already very high, this option may lead to
difficulty in fitting, which can also negatively
affect overall optimization quality. |
High Performance
with Maximum Placement
Effort |
Optimize synthesis for speed performance, with
additional placement optimization effort. |
Maximum Placement
Effort |
Makes the maximum effort to implement
placement, at the expsense of additional placement
optimization time. |
Extra Effort on
Retiming |
Retimer makes extra effort to retime registers
for the best performance. |
High Placement
Effort |
Makes high effort to implement placement, at
the expsense of additional placement optimization
time. |
High Power Effort |
The Compiler makes high effort
to optimize synthesis for low power. High Power Effort
increases synthesis run time. |
Aggressive Power |
Makes aggressive effort to
optimize synthesis for low power. The Compiler
further reduces the routing usage of signals with
the highest specified or estimated toggle rates,
saving additional dynamic power but potentially
affecting performance. |
High Placement Routability
Effort |
The Compiler makes high effort
to route the design at the potential expense of
design area, performance, and compilation time. The
Compiler spends additional time reducing routing
utilization, which can improve routability and also
saves dynamic power. |
Optimize Netlist for
Routability |
The Compiler implements
netlist modifications to increase routability at the
possible expense of performance. |
High Packing Routability
Effort |
The Compiler makes high effort
to route the design at the potential expense of
design area, performance, and compilation time. The
Compiler spends additional time packing registers,
which can improve routability and also saves dynamic
power. |
Aggressive Area |
The Compiler makes aggressive
effort to reduce the device area required to
implement the design at the potential expense of
design performance. |
Aggressive Compile Time |
Reduces the compile time
required to implement the design with reduced effort
and fewer performance optimizations. This option
also disables some detailed reporting functions.
Note: Turning on Aggressive Compile Time
enables Quartus® Prime Settings File (.qsf) settings which
cannot be overridden by other .qsf
settings.
|