Synplify Software Synopsys -Provided Logic Libraries Synopsys® software provides the altera logic library that is used for synthesizing and compiling VHDL and Verilog HDL designs. The altera library includes the following library files: Setting Up the Synplify Working Environment Creating a Design for Use with the Synplify Software Example of Creating a Black Box for a VHDL Custom Variation of a Intel FPGA IP with the Synplify Software Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software Creating and Instantiating a VHDL Function for Use with the Synplify Software About Using the Synplify Software with the Quartus Prime Software