PLL Compensation logic option

This logic option allows you to specify an output pin as a compensation target for a PLL in ZERO_DELAY_BUFFER or EXTERNAL_FEEDBACK mode, or an input pin or a group of input pins as compensation targets for a PLL in SOURCE_SYNCHRONOUS mode. If assigned to an output pin, the pin must be fed by the external clock output port of a PLL in a Stratix^® or Cyclone^® device, or the compensated clock output port of a PLL in other devices. Any other output pins fed by the same PLL generally are not delay compensated, especially if they have different I/O standards. If assigned to an input pin or a group of input pins, the input pins must drive input registers that are clocked by the compensated clock output port of a PLL in SOURCE_SYNCHRONOUS mode.

This option is ignored if it is applied to anything other than an output or input pin as described previously.

This option is available for supported device (Arria^® series, Cyclone^®III, Cyclone^®IV, and Stratix^®series) families.