VHDL Component Declaration

The following VHDL component declaration is located in the VHDL Design File (.vhd) Definition altera_mf_components.vhd in the <Quartus^® Prime installation directory>\libraries\vhdl\altera_mf directory.

component altasmi_parallel

        generic (

                intended_device_family  :       string := "unused";

                epcs_type       :       string := "EPCS4";

                page_size       :       natural := 1;

                port_bulk_erase :       string := "PORT_UNUSED";

                port_fast_read  :       string := "PORT_UNUSED";

                port_illegal_erase      :       string := "PORT_UNUSED";

                port_illegal_write      :       string := "PORT_UNUSED";

                port_read_address       :       string := "PORT_UNUSED";

                port_read_sid   :       string := "PORT_UNUSED";

                port_read_status        :       string := "PORT_UNUSED";

                port_sector_erase       :       string := "PORT_UNUSED";

                port_sector_protect     :       string := "PORT_UNUSED";

                port_shift_bytes        :       string := "PORT_UNUSED";

                port_wren       :       string := "PORT_UNUSED";

                port_write      :       string := "PORT_UNUSED";

                use_eab :       string := "ON";

                lpm_hint        :       string := "UNUSED";

                lpm_type        :       string := "altasmi_parallel"

        );

        port(

                addr    :       in std_logic_vector(23 downto 0);

                bulk_erase      : in std_logic := '0';

                busy    :       out std_logic;

                clkin   :       in std_logic;

                data_valid      : out std_logic;

                datain  :       in std_logic_vector(7 downto 0) := (others => '0');

                dataout :       out std_logic_vector(7 downto 0);

                epcs_id :       out std_logic_vector(7 downto 0);

                fast_read       :       in std_logic := '0';

                illegal_erase   :       out std_logic;

                illegal_write   :       out std_logic;

                rden    :       in std_logic;

                read    :       in std_logic := '0';

                read_address    :       out std_logic_vector(23 downto 0);

                read_sid        :       in std_logic := '0';

                read_status     :       in std_logic := '0';

                sector_erase    :       in std_logic := '0';

                sector_protect  :       in std_logic := '0';

                shift_bytes     :       in std_logic := '0';

                status_out      :       out std_logic_vector(7 downto 0);

                wren    :       in std_logic := '1';

                write   :       in std_logic := '0'

        );

end component;