Input Ports

otp_clk

Yes

Clock source.

Source clock to the OTP block.

otp_shiftnld

Yes

Shift and load signal.

When sampled as low, the loading operation is activated. The storage register loads the 128-bit OTP data parallel to the access register in one clock cycle. The loading operation is executed only once because the OTP data is retained in the access register after the first loading. When sampled as high, the shifting operation is activated. The otp_dout reads the OTP data serially from the access register. The data is read from the LSB to the MSB of the 128-bit OTP data.

otp_clken

No

Clock enable.

This optional port has the default value of 1 (high), which enables the shift and load operation of the OTP block.