Output Ports
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
ram_wren |
Yes |
Write enable signal to the RAM. |
When asserted high, the dataout port data is valid. |
dataout[] |
Yes |
Data sent to the external RAM. |
Output port [(width-1)..0] wide. The value of the dataout port corresponds to the data at the address specified by the ram_address port. |
ram_address[] |
Yes |
RAM address. |
|
rom_address[] |
No |
ROM address that connects to the external ROM. |
The rom_address port is applicable only in the external ROM mode. When the rom_address port is in use, connect the rom_address port to the address input port of the external ROM. |
rom_rden |
No |
Read enable signal that feeds back to the external ROM. |
The rom_rden port is applicable only in the external ROM mode. When asserted, the altmem_init Intel® FPGA IP generates a valid rom_address value. |
init_busy |
Yes |
RAM initialization from ROM in progress indicator. |
The init_busy signal remains active throughout the initialization process, and returns to an inactive state when initialization is complete. |