VHDL Component Declaration

The following VHDL component declaration is located in the VHDL Design File (.vhd) Definition ALTERA_MF_COMPONENTS.vhd in the <Quartus^® Prime installation directory>\libraries\vhdl\altera_mf directory.

component altmem_init

    generic (

        intended_device_family  :       string := "unused";

        init_file       :       string := "UNUSED";

        init_to_zero    :       string := "NO";

        numwords        :       natural;

        port_rom_data_ready     :       string := "PORT_CONNECTIVITY";

        rom_read_latency        :       natural := 1;

        width   :       natural;

        widthad :       natural;

    );

    port (

        clock   :       in std_logic := 0;

        clken   :       in std_logic := 1;

        datain  :       in  std_logic_vector (width - 1 DOWNTO 0) := (others => "0");

        dataout :       out std_logic_vector (width - 1 DOWNTO 0);

        init    :       in std_logic := 0;

        init_busy       :       out std_logic;

        ram_address     :       out std_logic_vector (widthad - 1 DOWNTO 0);

        ram_wren        :       out std_logic;

        rom_address     :       out std_logic_vector (widthad - 1 DOWNTO 0);

        rom_data_ready  :       in std_logic := 0;

        rom_rden        :       out std_logic;

    );

end component;