Input Ports
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
inclock |
Yes |
The clock port that drives the PLL. |
|
inclocken |
No |
The Phase-Locked Loop (PLL) Definition enable signal. |
When the inclocken port is high, the PLL drives the clock0 and clock1 output ports. When the inclocken port is low, GND drives the clock0 and clock1 output ports and the PLL goes out of lock. When the inclocken port goes high again, the PLL must relock. |
fbin |
No |
The external feedback input for the PLL. |
To complete the feedback loop, there must be a board-level connection between the fbin pin and the external clock output pin of the PLL. |