Input Ports

rx_datain[]

Yes

Data input port to the receiver.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

tx_datain[]

Yes

Data input signal to the transmitter.

Input port [TX_CHANNEL_WIDTH * NUMBER_OF_CHANNELS - 1..0] wide. Signal is 8, 10, 16, 20, 32, or 42bits wide.

rx_powerdown[]

No

Power down input for the receivers.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The rx_powerdown port connects to the clock management unit (CMU) primitive.

gxb_enable

No

quad Definition enable signal from the programmable logic device (PLD).

The gxb_enable signal must come from the pll_enable signal on the device.

gxb_powerdown[]

No

Quad reset signal from the PLD.

Input port [(NUMBER_OF_QUADS/NUM_BIT_PER_PROT) - 1..0] wide.

rx_invpolarity[]

No

Polarity inversion enable at the word aligner.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The rx_invpolarity input port is unavailable when the pipe8b10binvpolarity input port is in use.

tx_invpolarity[]

No

Polarity inversion enable after the 8B/10B encoder.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rateswitch

No

Switch between PCI Express Gen1 and Gen2.

The rateswitch input port is available only when the protocol is PCI Express (PIPE).

rx_revbyteorderwa[]

No

Byte order reversal enable from the word aligner.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_revbitorderwa[]

No

Bit order reversal enable from the word aligner.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_enabyteord[]

No

Dynamic byte ordering block enable.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_rmfifordena[]

No

Read operation enable for the rate matching FIFO.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The rx_rmfifordena input port is available only when the rate matching FIFO is not controlled by the internal state machine.

rx_rmfifowrena[]

No

Write operation enable for the rate matching FIFO.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The rx_rmfifowrena input port is available only when the rate matching FIFO is not controlled by the internal state machine.

rx_rmfiforeset[]

No

Rate matching FIFO reset.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_phfiforeset[]

No

Phase compensation FIFO reset.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

tx_phfiforeset[]

No

Phase compensation FIFO reset.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

tx_revparallellpbken[]

No

Dynamic reverse parallel feedback enable.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. Dynamically enables reverse parallel feedback. For the PCI Express (PIPE) protocol, the tx_revparallellpbken signal functionality is replaced by the tx_detectrxloop port.

rx_digitalreset[]

No

Digital reset signal to reset the digital portion of the receiver.

Input port [RX_DIGITALRESET_PORT_WIDTH - 1..0] wide.

tx_digitalreset[]

No

Digital reset signal to reset the digital portion of the transmitter.

Input port [TX_DIGITALRESET_PORT_WIDTH - 1..0] wide. When the bonding mode is 4-channel, the tx_digitalreset[] port and one signal per quad are required to drive the transmitter channels for the quad.

rx_analogreset[]

No

Analog reset signal to reset the analog portion of the receivers.

Input port [RX_DIGITALRESET_PORT_WIDTH - 1..0] wide.

rx_seriallpbken[]

No

Control signal that dynamically enables serial loopback.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. This port is available only when the operation mode is receiver and transmitter.

tx_detectrxloop[]

No

Receiver detect or loopback enable signal.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The value of the tx_detectrxloop input port is determined by the current power state.

powerdn[]

No

PCI Express (PIPE) power down directive.

Input port [NUMBER_OF_CHANNELS * 2 - 1..0] wide.

rx_coreclk[]

No

PLD clock network connection into the HSSI PCS receiver.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

tx_coreclk[]

No

PLD clock network connection into the HSSI PCS transmitter.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_cruclk[]

Yes

Clock input connection from the PLD source to the clock recovery unit (CRU) Definition.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

pll_inclk

Yes

Clock connection for the CMU Phase-Locked Loop (PLL) Definition.

rx_locktodata[]

No

Receiver PLL lock to the received data.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_locktorefclk[]

No

Receiver PLL lock to the reference clock.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_bitslip[]

No

Control signal to drop one bit.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The rx_bitslip[] port is used in manual bitslipping mode.

rx_enapatternalign[]

No

Word alignment enable.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_a1a2size[]

No

Specifies A1A2 or A1A1A2A2 commas.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. This port is available only when the protocol is SONET/SDH.

tx_ctrlenable[]

No

Specifies the 8-bit control word.

Input port [INT_TX_DWIDTH_FACTOR * NUMBER_OF_CHANNELS - 1..0] wide.

tx_forcedispcompliance[]

No

Forces the running disparity of the PIPE interface to negative.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

tx_forceelecidle[]

No

Forces the transmitter to send out an electrical idle signal.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The tx_forceelecidle[] signal can only be used when the protocol is PCI Express (PIPE).

fixedclk

No

Transmitter receiver detection.

A 125 MHz input clock signal must be provided for the fixedclk port.

pipe8b10binvpolarity[]

No

Polarity inversion enable at the 8B/10B decoder input.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. The pipe8b10binvpolarity port is available only when the protocol is PCI Express (PIPE).

aeq_togxb[]

No

Receiver analog test bus select. Specifies which analog test bus output port reports status.

Input port [(NUMBER_OF_CHANNELS * 4) - 1..0] wide.

tx_forcedisp[]

No

Transmitter force disparity enable.

Input port [INT_TX_DWIDTH_FACTOR * NUMBER_OF_CHANNELS - 1..0] wide. When asserted to high, the 8B/10B encoder encodes the word using the tx_dispval input port.

tx_dispval[]

No

Specifies whether the 8B/10B encoder codes the incoming word using positive or negative disparity.

Input port [INT_TX_DWIDTH_FACTOR * NUMBER_OF_CHANNELS - 1..0] wide.

cal_blk_clk

No

Calibration clock from the PLD to the calibration block.

The cal_blk_clk input port supports frequencies from 10MHz to 125MHz.

cal_blk_powerdown

No

Power down signal from the PLD to the calibration block.

Signal is active low. If cal_blk_powerdown is asserted to high, the signal is programmed with GND and the block is powered down.

reconfig_togxb[]

No

Specifies reconfigurable 3-bit input.

Input port [2..0] wide.

reconfig_clk[]

No

Reconfigurable clock input.

Input port [NUMBER_OF_QUADS - 1..0] wide.

tx_pipemargin[]

No

Selects transmitter de-emphasis under PCI Express Gen2 speeds 1"™b0: -6 dB 1"™b1: -3.5 dB.

Input port [NUMBER_OF_CHANNELS * 3 - 1..0] wide.

tx_pipedeemph[]

No

Controls the transmitter voltage swing level.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

tx_pipeswing[]

No

Selects transmitter voltage levels, that is, voltage output differential (VOD) settings.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

rx_prbscidenable[]

No

Enables the consecutive identical digits (CID) mode in the pseudo-random binary sequence (PRBS) generator.

Input port [NUMBER_OF_CHANNELS - 1..0] wide.

fixedclk_fast[]

No

Activates the soft-logic clock divider to lower the fixedclk port speed.

Input port [6 * NUMBER_OF_QUADS - 1..0] wide. This port is available when RX calibration is enabled and when in RX mode.

rx_seriallpbkin[]

No

Connects serial loopback input signal.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. This port is available only in receiver mode, and loopback_mode is precdr_rslb.

pll_inclk_rx_cruclk[]

No

PLL inclock bus for CMU PLL reconfiguration.

Input port [reconfig_pll_inclk_width - 1..0] wide. This port is available when the parameter reconfig_dprio_mode parameter is set to CMU PLL reconfiguration.

tx_revseriallpbkin[]

No

Connects reverse serial loopback input signal.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. This port is available only in TX mode, and loopback_mode is precdr_rslb or postcdr_rslb.

tx_bitslipboundaryselect[]

No

Indicates bit slip boundary select.

Input port [NUMBER_OF_CHANNELS * 5 - 1..0] wide.