Design contains failing path between Platform Designer interconnect components. This condition is due to the use of generic converter burst adapter.
Parameters
Name
Description
Type
Default Value
Min Value
Max Value
maximum_setup_slack
Reports a violation for timing paths that have a setup slack below the value of this parameter.
double
0.0
to_clock_filter
Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter.
string
*
minimum_number_of_adders
Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value.
integer
3
minimum_number_of_soft_mult_chains
Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value.
integer
2
Recommendation
To improve timing of the interconnect, use per-burst-type converter burst adapter. This implementation is faster than the generic burst adapter. Perform the following:
In Platform Designer, open the Platform Designer system that has this violation.
Figure 1. Platform Designer System
In the right-hand pane, go to DomainsInterconnect ParametersDomain tab.
Change the Burst adapter implementation parameter to use the Per-burst-type converter (faster, higher area) option using the drop-down menu.
Figure 2. Burst Adapter Implementation
Severity
Medium
Tags
Tag
Description
ip-parameterization
Design rule checks which look for parameterizable IP modules which may need to be adjusted to meet performance specifications.