TMC-20221: Nodes Failing Minimum Pulse Width Due to Clock Pulse Collapse
Description
Violations of this rule identify nodes that fail minimum pulse width due to clock pulse collapse. Duty cycle distortion can cause a clock pulse to collapse inside the clock path enroute to the destination node. If this condition occurs, the clock signal fails to reach the destination.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_pulse_width_slack | Reports a violation for timing endpoints that have a minimum-pulse-width slack below the value of this parameter. | double | 0.0 |
Recommendation
- Reduce the total delay of the clock path.
- Relax the clock constraint(s).
- Minimize any logic or local routing used in the clock path.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| minimum-pulse-width | Design rule checks related to minimum pulse width. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®