TMC-20200: Paths Failing Setup Analysis with Impossible Requirements
Description
Violations of this rule identify paths with an "intrinsic margin" below the value of the maximum_setup_slack parameter.
Timing paths may fail setup analysis without any contributions from cell delay, interconnect delay, or clock skew. If those components are removed from the overall slack, the remaining slack is the combination of clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These requirements together constitute a path's intrinsic margin. A negative intrinsic margin is an impossible requirement to meet.
For example, consider a path with a combined μtco and μtsu that exceeds the target clock period. Such a path has a negative intrinsic margin and has an impossible setup requirement. Relax the setup relationship to close timing.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Restructure or re-constrain the path to increase the intrinsic margin using one of the following:
- Adjust SDC constraints to relax the path's setup constraint.
- If the launch and latch clocks are different, ensure their relationship is properly constrained.
- If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| intrinsic-margin | Design rule checks which use the Intrinsic Margin metric (slack ignoring cell delay, IC delay and clock skew) to diagnose potential timing issues on failing paths. |
| impossible-requirements | Design rule checks which check the requirements on failing timing paths and flag those which fail by construction. |
| sdc | Design rule checks related to SDC validity checking. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX