RES-50003: Asynchronous Reset with Insufficient Constraints
Description
Violations of this rule identify asynchronous reset synchronizer chains where the reset signal feeding its registers has insufficient timing constraints. The release of the asynchronous signal feeding a reset synchronizer chain must be constrained in a way that prevents the Timing Analyzer from treating it as a timed, synchronous transfer.
Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:
- The reset signal is from an unconstrained input
- The clock domain of the reset signal is unrelated/asynchronous to the latching domain of the register being reset
Recommendation
Synchronize the release of asynchronous reset signals with a reset synchronizer chain. Use Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) to generate a reset synchronizer chain.
Refer to the documentation of Insert Template Dialog Box for instructions on adding (or instantiating) this macro.
To resolve the violation without using the Asynchronous Reset Synchronizer Parameterizable Macro, constrain the reset signal feeding a reset chain with a set_false_path or set_clock_groups constraint, or relax the timing on the transfer with a set_max_delay constraint with a value greater than the latch clock's period. Applying a false path constraint with flag "-no_synchronizer" is insufficient to satisfy this rule. Applying a max delay of any other value is insufficient to satisfy this rule.
Severity
High
Tags
Tag | Description |
---|---|
synchronizer | Design rule checks related to synchronizer chains. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®