RES-50001: Asynchronous Reset Is Not Synchronized
Description
Violations of this rule identify unsynchronized asynchronous reset signal sources that reset registers. When using an asynchronous reset, the release of the reset signal must be synchronous with the register being reset. Otherwise, the register may experience metastability upon reset release.
Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:
- The reset signal is from an unconstrained input
- The clock domain of the reset signal is unrelated or asynchronous to the latching domain of the register being reset
Recommendation
Synchronize the release of asynchronous reset signals with a reset synchronizer chain. Use Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) to generate a reset synchronizer chain.
Refer to the documentation of Insert Template Dialog Box for instructions on adding (or instantiating) this macro.
To resolve the violation without using the Asynchronous Reset Synchronizer Parameterizable Macro, ensure that the reset signal feeds the asynchronous reset pins of a sequence of two or more registers, with no fan-out in between them, and with the head of the chain fed by a constant. You can use the output of the last register as a reset signal that is synchronous with the clock domain of the chain.
Severity
High
Tags
Tag | Description |
---|---|
synchronizer | Design rule checks related to synchronizer chains. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®