RDC-50003: Multiple Asynchronous Reset Synchronizers in the Same Clock Domain

Description

Violations of this rule identify the clock domain(s) that has more than one asynchronous reset synchronizers. Since asynchronous reset synchronizers may not come out of reset on the same clock cycle, the logic reaching the nodes that belong in multiple reset domains may contain both active and reset data at the same time.

Figure 1. Path Between Registers in Different Reset Domains.
Figure 2. Registers in Different Reset Domains Converging through Combinational Logic.
Figure 3. Path Between Registers in Different Reset Domains.
Figure 4. Registers in Different Reset Domains Converging through Combinational Logic.

Recommendation

Replace the existing RDC circuit with the Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst).

Refer to the documentation of Insert Template Dialog Box for instructions on adding (or instantiating) this macro.

To resolve the violation, use the output of the same reset synchronizer chain for resetting all registers in a fan-out cone. If the reset signal is timing critical, add a pipelined reset tree after the reset synchronizer to close timing.

If the design uses mutiple reset synchronizers that converge by employing tokens or handshaking across different reset domain crossings, then you can ignore or waive the rule.

Figure 5. Pipelined Reset Tree After Reset Synchronizer

Severity

Medium

Tags

Tag Description
reset-usage Design rule checks related to safe resets or appropriate use of reset modes.
reset-reachability Design rule checks related to reachability analysis of reset signals, including convergence of mutiple reset signals.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®