CLK-30034: Clock Pairs Missing Logically Exclusive Clock Group Assignment
Description
Violations of this rule identify clock pairs which are missing constraints. (1) Two generated clocks on a LUT output are missing a logically exclusive clock group assignment. (2) Two clocks pass through a LUT are missing generated clocks on the LUT output and a logically exclusive clock group assignment on the generated clocks.
Recommendation
Add create_generated_clock assignments on the LUT output and a set_clock_group -logically_exclusive assignment on the generated clocks.
Severity
High
Tags
| Tag | Description |
|---|---|
| sdc | Design rule checks related to SDC validity checking. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®