CLK-30029: Invalid Clock Assignments
Description
Violations of this rule identify registers that are clocked by both the rising and falling edges of the same clock.
Recommendation
Remove one of the clock edge assignments. If necessary, create two separate clocks that have similar settings, and assign to the same node.
Severity
High
Tags
| Tag | Description |
|---|---|
| sdc | Design rule checks related to SDC validity checking. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®