CDC-50008: CDC Bus Constructed with Multi-bit Synchronizer Chains

Description

Violations of this rule identify multi-bit synchronizer chains that form a CDC bus. This CDC topology is only valid for buses that transfer Gray-coded data.

Figure 1. Synchronized CDC Bus Transfer.. The following figure shows a synchronized CDC bus transfer, which must be Gray-coded to work correctly:

Recommendation

If the bus does not transfer Gray-coded data, change its implementation to incorporate a control signal since synchronizer chains are not sufficient to ensure that all bits of the bus latch on the same clock cycle.

If you have verified that this bus transfers Gray-coded data, you can waive this violation or apply the QSF assignment VERIFIED_GRAY_CODED_BUS_DESTINATIONS ON to all of the multi-bit synchronizer chain's head registers. For example, if the head registers for the multi-bit synchronizer bus are dst_reg[3:0], you can apply the QSF assignment to dst_reg[*] in the Assignment Editor, or add the following line to your project's .qsf file: set_instance_assignment -name VERIFIED_GRAY_CODED_BUS_DESTINATIONS ON -to dst_reg[*], or declare the assignment using altera_attribute in the HDL file. In Verilog, you can specify: (* altera_attribute = "-name VERIFIED_GRAY_CODED_BUS_DESTINATIONS ON" *) reg [3:0] dst_reg, and in VHDL, you can specify: signal dst_reg : std_logic_vector (3 downto 0); attribute altera_attribute : string; attribute altera_attribute of dst_reg : signal is "-name VERIFIED_GRAY_CODED_BUS_DESTINATIONS ON"; to declare the head registers of the synchronizer bus.

Severity

Low

Tags

Tag Description
synchronizer Design rule checks related to synchronizer chains.
cdc-bus Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®