CDC-50007: CDC Bus Constructed with Multi-bit Synchronizer Chains with Insufficient Constraints

Description

Violations of this rule identify multi-bit synchronizer chains that form a CDC bus with insufficient constraints. Without proper constraints, all bits of such a bus may not latch on the same clock cycle.

Figure 1. A synchronized CDC bus transfer in need of constraints.. To prevent a CDC-50007 violation, there must be skew and net delay constraints on the transfers from the orange registers to the leftmost blue registers in the following figure:

Recommendation

If the bus does not transfer Gray-coded data, change its implementation to incorporate a control signal since synchronizer chains are not sufficient to ensure that all bits of the bus settle on the same clock cycle.

If the bus transfers Gray-coded data, apply a set_max_skew constraint on the bits of the synchronizer bus to ensure that all bits latch on the same clock cycle. The value of the skew constraint must be equal to or lower than either the source or destination clock period, whichever is lower. This can be accomplished with the following constraint:

set_max_skew

Also, ensure that a set_net_delay constraint or a set_data_delay constraint exists on the bits of the bus to limit their allowable delay. The value of the net delay constraint or data delay constraint must be equal to or lower than the destination clock period. This can be accomplished with the following constraint:

set_net_delay

Severity

High

Tags

Tag Description
synchronizer Design rule checks related to synchronizer chains.
cdc-bus Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®