CDC-50005: CDC Bus Constructed with Multi-bit Synchronizer Chains of Different Lengths

Description

Violations of this rule identify multi-bit synchronizer chains with different chain lengths that form a CDC bus. Data does not exit the synchronizer chain on the same clock cycle.

Figure 1. An imbalanced CDC bus transfer.. The following figure shows an example of an imbalanced CDC bus. The bus is imbalanced because one bit forms a two-stage synchronizer, and another bit lacks a synchronizer. To prevent a CDC-50005 violation, both registers must form a synchronizer of the same length.

Recommendation

If the bus transfers gray-coded data, ensure that the destination of each bit forms a chain of two or more registers, and that each chain contains the same number of registers. This allows each bit of data to exit the register chains on the same clock cycle.

If the bus does not transfer gray-coded data, synchronizer chains are not sufficient to ensure that all bits of the bus latch on the same clock cycle. Replace the existing CDC handshake circuit with the Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync).

Refer to the documentation of Insert Template Dialog Box for instructions on adding (or instantiating) this macro.

To resolve the violation without replacing the circuit with the Bus Synchronizer Parameterizable Macro, remove the synchronizer chains and change its implementation to incorporate a control signal, since synchronizer chains are not sufficient to ensure that all bits of the bus latch on the same clock cycle.

Figure 2. A balanced CDC bus transfer.

Severity

High

Tags

Tag Description
synchronizer Design rule checks related to synchronizer chains.
cdc-bus Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®