CDC-50004: MUX-type CDC Transfer with Insufficient Constraints
Description
Violations of this rule identify a CDC transfer controlled by a MUX or a MUX-like topology with insufficient timing constraints. Without proper constraints, all bits of such a topology may not latch on the same clock cycle.
Recommendation
If you are using handshake for clock domain crossing, replace the existing CDC handshake circuit with the Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync).
Refer to the documentation of Insert Template Dialog Box for instructions on adding (or instantiating) this macro.
To resolve the violation without replacing the circuit with the Bus Synchronizer Parameterizable Macro, apply an instance assignment of Synchronization Register Chain Length = 1 on the head of a MUX-type CDC to prevent downstream registers from being treated as a synchronizer chain. Next, if the transfer forms a multi-bit bus, apply a set_max_skew constraint on the bits of the bus to ensure that all bits latch on the same clock cycle. The value of the skew constraint must be equal to or lower than either the source or destination clock period, whichever is lower. This can be accomplished with the following constraint:
Also, for all CDC widths, apply a set_data_delay constraint on the bits of the transfer to limit their allowable delay. The value of the data delay constraint must be equal to or lower than the destination clock period. This can be accomplished with the following constraint:
Severity
High
Tags
| Tag | Description |
|---|---|
| cdc-bus | Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®