IP Cores IP Catalog and Parameter Editor Intel FPGA IP Cores/LPM Clear Box Command-Line Tool altsquare Intel FPGA IP altstratixii_oct Intel FPGA IP altsyncram Intel FPGA IP altufm_i2c Intel FPGA IP altufm_none Intel FPGA IP altufm_osc Intel FPGA IP altufm_parallel Intel FPGA IP altufm_spi Intel FPGA IP altasmi_parallel Intel FPGA IP csdpram Intel FPGA IP csfifo Intel FPGA IP divide Intel FPGA IP lpm_and Intel FPGA IP lpm_bustri Intel FPGA IP lpm_clshift Intel FPGA IP lpm_constant Intel FPGA IP lpm_decode Intel FPGA IP lpm_dff Intel FPGA IP lpm_ff Intel FPGA IP lpm_inv Intel FPGA IP lpm_latch Intel FPGA IP lpm_mux, mux and busmux Intel FPGA IP lpm_or Intel FPGA IP lpm_ram_dp Intel FPGA IP lpm_ram_dq Intel FPGA IP lpm_ram_io Intel FPGA IP lpm_rom Intel FPGA IP lpm_shiftreg Intel FPGA IP lpm_tff Intel FPGA IP lpm_xor Intel FPGA IP Macrofunctions sld_signaltap IP Core Virtual JTAG Interface (VJI) Intel FPGA IP Provides access to the device through the JTAG interface. altera_soft_core_jtag_io Intel FPGA IP Generating a Netlist for Third-Party Synthesis Tools from Megafunctions and Intel FPGA IP Functions Clock Enable Signal Equalizer Control Pre-emphasis Control Signal Intel-Specific Parameters "UNUSED" Parameter Value WYSIWYG Atom Names Unavailable for Use as Intel FPGA IP Instance Names Example of Pipeline Stages in the Divide Function Example of Using the Full Output as an Extra Bit for the usedw[ ] Output alt3pram Intel FPGA IP altgx Intel FPGA IP alt_oct IP Core altclklock IP Core altdll Intel FPGA IP RAM: 2-PORT Intel FPGA IP Parameterized dual-port RAM Intel® FPGA IP. altdq Intel FPGA IP altdq_dqs Intel FPGA IP altdqs Intel FPGA IP altmem_init Intel FPGA IP ALTMEMPHY Intel FPGA IP altotp Intel FPGA IP altserial_flash_loader Intel FPGA IP altsource_probe Intel FPGA IP