To perform a simulation of a Verilog HDL design with command-line commands using the Xcelium* simulator

  1. If you have not already done so, set up the Xcelium* simulator working Environment.
  2. To create a work library in the project directory, type the following command at the command prompt:
    mkdir <work library>
    Note:

    Intel recommends using the Xcelium™ (Verilog or VHDL) default library names when you create a library. You should name the Xcelium software libraries as follows:

    • When you run the Xcelium software independently from the Quartus® Prime software, you should name your library work.
    • When you run the Xcelium software automatically from the Quartus® Prime software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.
  3. Copy the cds.lib and hdl.var files from the Xcelium install directory to the /<project directory>/simulation/xmsim directory.
  4. To compile the appropriate project files into the work library, type the following commands at the command prompt from within the project directory:
    xmvlog<testbench file>.v
xmvlog<design name>.v
  5. To elaborate and simulate the design, type the following command at the command prompt:
    xmelab <work library>.<top-level entity name>  
xmsim <work library>.<top-level entity name>