AHDL Function Prototype (port name and order also apply to Verilog HDL)

The following AHDL function prototype is located in the AHDL Include File (.inc) Definitionaltclklock.inc located in the <Quartus^® Prime installation directory>\libraries\megafunctions directory.

FUNCTION altclklock(inclock, inclocken, fbin)

        WITH (INCLOCK_PERIOD, INCLOCK_SETTINGS,

                VALID_LOCK_CYCLES, INVALID_LOCK_CYCLES,

                VALID_LOCK_MULTIPLIER, INVALID_LOCK_MULTIPLIER,

                OPERATION_MODE,

                CLOCK0_BOOST, CLOCK0_DIVIDE, CLOCK0_SETTINGS,

                CLOCK1_BOOST, CLOCK1_DIVIDE, CLOCK1_SETTINGS,

                OUTCLOCK_PHASE_SHIFT, CLOCK0_TIME_DELAY,

                CLOCK1_TIME_DELAY, CLOCK2_BOOST, CLOCK2_DIVIDE,

                CLOCK2_SETTINGS, CLOCK2_TIME_DELAY, CLOCK_EXT_BOOST,

                CLOCK_EXT_DIVIDE, CLOCK_EXT_SETTINGS, CLOCK_EXT_TIME_DELAY,

                INTENDED_DEVICE_FAMILY)

        RETURNS (clock0, clock1, locked, clock2, clock_ext);