TMC-20202: Paths Failing Setup Analysis with High Logic Delay

Description

Violations of this rule identify paths with a "logic-only slack" below the maximum_setup_slack threshold parameter

Timing paths may fail setup analysis without any delay contributions from fabric interconnect delay or clock skew. If those components are removed from the overall slack, the remaining slack is the path's logic delay (cell delay + local interconnect delay), as well as the combination of the clock relationship, endpoint microparameters, SDC constraints, and other such requirements. These components together constitute a path's logic-only slack. A negative logic-only slack implies that the path's logic levels must be reduced or its requirements must be relaxed to meet timing.

For example, consider a path with a combined μtco, μtsu, cell delay, and local interconnect delay that together exceeds the target clock period. Such a path is likely to fail setup analysis, and as such its "logic-only-only slack" is negative. Reduce logic levels on the path or relax its setup requirements to close timing.

Parameters

Name	Description	Type	Default Value
maximum_setup_slack	Reports a violation for timing paths that have a setup slack below the value of this parameter.	double	0.0
to_clock_filter	Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter.	string	*
minimum_number_of_adders	Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value.	integer	3
minimum_number_of_soft_mult_chains	Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value.	integer	2

Recommendation

Restructure the path to increase its intrinsic margin or reduce the logic delay on the path:

Add pipeline registers to break up deep combinational clouds.
Refactor logic on the path to reduce logic levels.
Ensure register retiming optimization is unblocked on the path.
Adjust SDC constraints to relax the path's setup constraint.
If the path's endpoints involve DSP, RAM, or I/O blocks, ensure that those blocks are sufficiently registered.
If the launch and latch clocks are different, ensure their relationship is properly constrained.

Severity

Medium

Tag	Description
intrinsic-margin	Design rule checks which use the Intrinsic Margin metric (slack ignoring cell delay, IC delay and clock skew) to diagnose potential timing issues on failing paths.
logic-levels	Design rule checks which flag potentially problematic amounts of logic on a timing path.

Device Family