CDC-50003: CE-Type CDC Transfer with Insufficient Constraints

Description

Violations of this rule identify a CDC transfer synchronized by DFFE (D Flip-Flop with Enable) registers with insufficient timing constraints. Without proper constraints, all bits of such a topology may not latch on the same clock cycle.

Figure 1. Multi-bit CE-type CDC transfer in need of constraints.. In the following figure, the enable signal is synchronized, but the N-bit CDC transfer requires constraints to limit skew and datapath delay.

Recommendation

Apply an instance assignment of Synchronization Register Chain Length = 1 on the head of a CE-type CDC to prevent downstream registers from being treated as a synchronizer chain. Next, if the transfer forms a multi-bit bus, apply a set_max_skew constraint on the bits of the bus to ensure that all bits latch on the same clock cycle. The value of the skew constraint must be equal to or lower than either the source or destination clock period, whichever is lower. This can be accomplished with the following constraint:

set_max_skew

Also, for all CDC widths, apply a set_net_delay constraint or a set_data_delay constraint on the bits of the transfer to limit their allowable delay. The value of the net delay constraint or data delay constraint must be equal to or lower than the destination clock period. This can be accomplished with the following constraint:

set_net_delay

Severity

High

Tags

Tag Description
cdc-bus Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®