Programmable Power Technology Tiles Definition

Programmable Power Technology uses on-chip voltage regulators to enable Stratix^® III, Stratix^® IV, and Stratix^® V core logic to be programmed at the tile level for high-speed mode or low-power mode configuration. Tiles are defined as:

• A combination of a LAB and MLAB pair
• A DSP block
• A memory block
• A column I/O interface

Tiles can be configured to operate in high-speed mode or low-power mode.

The Intel^® Quartus^® Primesoftware automatically controls which tile should operate at high-speed mode or low-power mode based on the timing constraints specified for the design. The power optimization, Programmable Power Maximum High-Speed Fraction of Used LAB Tiles and Programmable Power Technology Optimization options available in the Advanced Settings (Fitter) dialog box control the high-speed mode or low-power mode tiles configuration along with other power optimization techniques implemented at the Fitter level.