name characters Definition
The characters A to Z, a to z, 0 to 9, slash (/), dash (-), and underscore (_) are legal for Intel® Quartus® Prime breakpoint, chip, clique, directory, file, project, revision, group (bus), node, parameter, pin, pinstub, and quoted and unquoted symbolic names, with the exceptions listed below.
| Item | Name Character Exception |
|---|---|
| file name | No slash (/) is permitted. Case is significant on Linux workstations; all file names should be in lowercase letters. Case is also significant in Verilog HDL files. |
| project name | No slash (/) is permitted. Case is significant on Linux workstations. |
| revision name | No slash (/) is permitted. Case is significant on Linux workstations. |
| single-range group (bus) name | No slash (/) is permitted; the bus identifier cannot end with a digit. The name is followed by a range of numbers or arithmetic expressions in brackets. The start and end of the range are separated by two periods. For example, group a[3..1] consists of the nodes a3, a2, and a1. In Block Editor files only, sequential bus names can also include a series of single-range bus names. For example, a[8..0],dout[6..4]. |
| design partition name | Partition names can have a maximum of 1024 characters. The name can consist only of alphanumeric characters, the colon (:), the pipe (|), and the underscore ( _ ) characters. |
| dual-range group (bus) name | Same as single-range group names, with two ranges of numbers or arithmetic expressions in brackets. For example, a[6..3][4..0]. |
| sequential group (bus) name | The name consists of a series of comma-separated node names enclosed in parentheses. For example, group (a, b, c) consists of the nodes a, b, and c. In Block Editor files, parentheses are not used. |
| unquoted symbolic name (AHDL) | No dash (-) is permitted. Names cannot consist entirely of digits. AHDL keywords cannot be used. |
| Verilog HDL identifiers | No slash (/) or dash (-) is permitted. Dollar signs ($) are permitted. Names cannot begin with a digit or $. Case is significant. Verilog HDL keywords cannot be used. |
| VHDL names | No slash (/) or dash (-) is permitted. The name must start with a letter, cannot end with an underscore (_), and cannot contain two underscores (_ _) in a row. VHDL keywords cannot be used. |