Adaptive Logic Module (ALM) Definition

The Adaptive Logic Module (ALM) is a basic building block that maximizes performance and resource usage in Intel® FPGAs. Each ALM has the following characteristics:

  • Supports up to eight inputs and eight outputs.
  • Contains two or four register logic cells (lc_ff).
  • Contains two combinational logic cells (lc_comb).
  • Contains two dedicated full adders, a carry chain, a register chain, and a 64-bit LUT mask.

The ALM operates in adaptive combinational logic mode (normal mode), extended LUT mode (7-input function mode), arithmetic mode, and shared arithmetic mode.

The Intel® Stratix® 10 ALM has a high register count with 4 registers per 8-input fracturable LUT. The ALM operating in conjunction with the new HyperFlex architecture enables Intel® Stratix® 10 devices to maximize core performance at very high core logic utilization. The Intel® Stratix® 10 ALM implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization.

You can implement the following types of functions in a single ALM:

  • Two independent 4-input functions
  • An independent 5-input function and an independent 3-input function
  • A 5-input function and a 4-input function, if they share one input
  • Two 5-input functions, if they share two inputs
  • An independent 6-input function
  • Two 6-input functions, if they share four inputs and share function
  • Some 7-input functions

The devices in the Intel Agilex FPGA portfolio use an enhanced adaptive logic module (ALM) similar to previous generation Intel FPGAs. The enhanced ALM allows for efficient implementation of logic functions and easy IP conversion between Intel Agilex FPGA portfolio devices and Intel® Arria® 10 FPGAs and Intel® Stratix® 10 FPGAs.

Figure 1. ALM Block Diagram. This figure shows the ALM with 8-input fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.
Table 1. Key Features and Capabilities of the Intel Agilex FPGA Portfolio ALM
Key Feature Capability
High register count Together with the second generation Intel® Hyperflex™ architecture, the four registers per 8-input fracturable LUT enables maximized core performance at very high core logic utilization.
ALM operating modes Optimize core logic utilization by implementing an extended 7-input logic function, a single 6-input logic function, or two smaller independent functions (for example, two 4-input functions).
Two clock sources Two clock sources per ALM generate two normal clocks and two delayed clocks to drive the ALM registers, resulting in more clock domains and time-borrowing capability.
Additional LUT outputs Additional fast 6-LUT and 5-LUT outputs for combinatorial functions improve critical path for logic cascade.
Improved register packing The improved register packing, including 5-input LUT with two packed register paths, results in more efficient usage of the fabric area and improved critical path.
Latch mode support The ALM supports latch mode in the address latch enable.

The Intel® Quartus® Prime software capitalizes on the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel® Quartus® Prime software simplifies design reuse as the software automatically maps legacy designs into the ALM architecture of the devices in the Intel Agilex FPGA portfolio.