Save intermediate synthesis results

• Save a node-level netlist of the entire design into a persistent source file— Directs the Compiler Database Interface to save synthesis results for the current design's top-level entity as an atom-based netlist in Verilog Quartus Mapping File (.vqm) Definition format during a full compilation.

• File name— Specifies the name of the Verilog Quartus Mapping File that the Compiler Database Interface generates when saving synthesis results. By default, the Intel^® Quartus^® Prime software places the Verilog Quartus Mapping File in the atom_netlists directory under the current project directory. You can direct the Intel^® Quartus^® Prime software to place this file in a different directory by specifying the directory path in the File name box. However, the Intel^® Quartus^® Prime software cannot place the Verilog Quartus Mapping File in the same directory as the current project.

If you are already compiling only from EDIF Input File (.edf) Definition or Verilog Quartus Mapping Files, which are atom-based netlists, you do not need to save synthesis results with the Intel^® Quartus^® Prime software. You may need to save synthesis results if you use a combination of atom-based netlists and other source files, such as files that the IP Catalog generates.