VHDL Component Declaration
The following VHDL component declaration is located in the VHDL Design File (.vhd) Definition ALTERA_MF_COMPONENTS.vhd in the <Intel® Quartus® Prime installation directory>\libraries\vhdl\altera_mf directory.
component altdq generic ( ddioinclk_input : string := "NEGATED_INCLK"; intended_device_family : string := "unused"; extend_oe_disable : string := "OFF"; invert_input_clocks : string := "ON"; number_of_dq : natural; oe_reg : string := "UNREGISTERED"; power_up_high : string := "OFF"; lpm_hint : string := "UNUSED"; lpm_type : string := "altdq" ); port( aclr : in std_logic := '0'; aset : in std_logic := '0'; datain_h : in std_logic_vector(number_of_dq-1 downto 0); datain_l : in std_logic_vector(number_of_dq-1 downto 0); dataout_h : out std_logic_vector(number_of_dq-1 downto 0); dataout_l : out std_logic_vector(number_of_dq-1 downto 0); ddioinclk : in std_logic := '0'; inclock : in std_logic; inclocken : in std_logic := '1'; oe : in std_logic := '1'; outclock : in std_logic; outclocken : in std_logic := '1'; padio : inout std_logic_vector(number_of_dq-1 downto 0) ); end component;