Output Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
rx_dataout[] |
Yes |
Recovered data streams as parallel data out of the receiver into the PLD source. |
Output port [RX_CHANNEL_WIDTH * NUMBER_OF_CHANNELS - 1..0] wide. |
tx_dataout[] |
Yes |
Serial data output signal from the transmitter. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_clkout[] |
No |
Receiver output clock. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
tx_clkout[] |
No |
Transmitter output clock. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. The tx_clkout[] port is available only with non-bonded modes. |
rx_pll_locked[] |
No |
Receiver PLL is in locked mode with the reference clock indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_freqlocked[] |
No |
Receiver PLL is in locked mode with the receiver data indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_rlv[] |
No |
Channel violation of the specified rx_run_length port indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_syncstatus[] |
No |
Output status from the pattern detector and word aligner indicator. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0] wide. |
rx_patterndetect[] |
No |
Pattern detection indicator. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0] wide. |
rx_ctrldetect[] |
No |
8B/10B decoder detection control code indicator. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. |
rx_errdetect[] |
No |
8B/10B decoder detection error code indicator. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. |
rx_disperr[] |
No |
8B/10B decoder detection disparity code indicator. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. |
rx_runningdisp[] |
No |
Status signal. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. Specifies whether the running disparity of the 8B/10B decoder is positive or negative. |
rx_rmfifodatainserted[] |
No |
Rate matching FIFO data insertion status signal. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. |
rx_rmfifodatadeleted[] |
No |
Rate matching FIFO data deletion status signal. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. |
rx_bisterr[] |
No |
Error status signal for built-in self test (BIST). |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_bistdone[] |
No |
Self test complete signal. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_a1a2sizeout[] |
No |
Signal after the rx_a1a2size signal is synchronized to the word aligner module. |
Output port [NUMBER_OF_CHANNELS *int_rx_dwidth_factor- 1..0]wide. This port is available only when the protocol is set toSONET. |
rx_signaldetect[] |
No |
Signal is at data input detection indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
pipestatus[] |
No |
3-bit PIPE interface status signal to the PLD. |
Output port [NUMBER_OF_CHANNELS * 3] wide. |
pipedatavalid[] |
No |
Valid data from the receiver indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
pipeelecidle[] |
No |
Electrical idle detection status signal. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
pipephydonestatus[] |
No |
PIPE power state transition completion indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
rx_channelaligned[] |
No |
Deskew alignment status output indicator. |
Output port [NUMBER_OF_QUADS - 1..0] wide. Specifies whether the channels are aligned. This port is available only when the PROTOCOL value is set to XAUI. |
pll_locked[] |
No |
CMU Phase-Locked Loop (PLL) Definition are locked to the respective input clock signal indicator. |
Output port [NUMBER_OF_QUADS - 1..0] wide. Output port is one bit wide per quad. |
coreclkout[] |
No |
Source clock output to the PLD from the CMU clock divider. |
Output port [NUMBER_OF_QUADS - 1..0] wide. |
rx_dataoutfull |
No |
64-bit output port from receiver during reconfiguration. |
Output port [(NUMBER_OF_CHANNELS * 64) - 1..0] wide. This is only applicable when the RECONFIG_DPRIO_MODE parameter value is set to NONE. |
rx_recovclkout[] |
No |
Recovered clock output from the receiver. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. Note:
This is an advanced option available only through the command line. |
rx_a1detect[] |
No |
A1 detect signal from the word aligner. |
Output port [(NUMBER_OF_CHANNELS * INT_RX_WORD_ALIGNER_NUM_BYTE) - 1..0] wide. Specifies that the A1 pattern in the programmed 16-bit A1A2 pattern is detected. Note:
This is an advanced option available only through the command line. |
rx_a2detect[] |
No |
A2 detect signal from the word aligner. |
Output port [(NUMBER_OF_CHANNELS * INT_RX_WORD_ALIGNER_NUM_BYTE) - 1..0] wide. Specifies that the A2 pattern in the programmed 16-bit A1A2 pattern is detected. Note:
This is an advanced option available only through the command line. |
rx_k1detect[] |
No |
K1 detect signal from the word aligner for the upper 10 bits. |
Output port [(NUMBER_OF_CHANNELS * INT_RX_WORD_ALIGNER_NUM_BYTE) - 1..0] wide. Specifies that the K1 pattern in the programmed 20-bit K1K2 pattern is detected. Note:
This is an advanced option available only through the command line. |
rx_k2detect[] |
No |
K2 detect signal from the word aligner for the upper 10 bits. |
Output port [(NUMBER_OF_CHANNELS 2) - 1..0] wide. Specifies that the K2 pattern in the programmed 20-bit K1K2 pattern is detected. Note:
This is an advanced option available only through the command line. |
rx_rmfifoempty[] |
No |
Rate matching FIFO empty indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. When asserted to high, the rate matching FIFO is empty. Note:
This is an advanced option available only through the command line. |
rx_rmfifofull |
No |
Rate matching FIFO full indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. When asserted to high, the rate matching FIFO is full. Note:
This is an advanced option available only through the command line. |
rx_rmfifoalmostempty[] |
No |
Rate matching FIFO almost empty indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. When asserted to high, the rate matching FIFO has reached the value specified by the RX_RATE_MATCH_ALMOST_EMPTY_THRESHOLD parameter. Note:
This is an advanced option available only through the command line. |
rx_rmfifoalmostfull[] |
No |
Rate matching FIFO almost full indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. When asserted to high, the rate matching FIFO has reached the value specified by the RX_RATE_MATCH_ALMOST_FULL_THRESHOLD parameter. Note:
This is an advanced option available only through the command line. |
rx_byteorderalignstatus[] |
No |
Signal from byte ordering block successful alignment indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. Note:
This is an advanced option available only through the command line. |
rx_phfifooverflow[] |
No |
Phase compensation FIFO overflow output signal. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. Note:
This is an advanced option available only through the command line. |
rx_phfifounderflow[] |
No |
Phase compensation FIFO underflow output signal. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. Note:
This is an advanced option available only through the command line. |
debug_tx_phase_comp_fifo_error[] |
No |
OR operation on the tx_phfifounderflow and tx_phfifooverflow ports indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. |
reconfig_fromgxb[] |
No |
Reconfiguration output to the PLD. |
Output port [NUMBER_OF_QUADS - 1..0] wide. |
aeq_fromgxb[] |
No |
Analog test bus output to the PLD. |
Output port [(NUMBER_OF_CHANNELS * 2) - 1..0] wide. |
tx_phfifooverflow[] |
No |
Phase compensation FIFO overflow indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. Note:
This is an advanced option available only through the command line. |
tx_phfifounderflow[] |
No |
Phase compensation FIFO underflow indicator. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. Note:
This is an advanced option available only through the command line. |
cal_blk_calibrationstatus[] |
No |
5-bit 1-Ohm calibration result status signal. |
Output port [4..0] wide. Note:
This is an advanced option available only through the command line. |
rx_bitslipboundaryselectout[] |
No |
Bit slip boundary select output. |
Output port [NUMBER_OF_CHANNELS * 5- 1..0] wide. |
rx_revseriallpbkout[] |
No |
Reverse serial loopback output signal. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. This port is available only in RX mode and loopback_mode is precdr_rslb or postcdr_rslb. |
pll_locked_alt[] |
No |
Signal to indicate that the alternate CMU PLL is locked to the respective input clock signal. |
Output port [pll_control_width - 1..0] wide. |
tx_seriallpbkout[] |
No |
Serial loopback output signal. |
Output port [NUMBER_OF_CHANNELS - 1..0] wide. This port is available only in TX mode and loopback_mode is precdr_rslb. |