Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
data[] |
Yes |
Data input to the memory. |
Input port WIDTH wide. |
rdaddress_a[] |
Yes |
Read address input to the memory. |
Input port WIDTHAD wide. |
rdaddress_b[] |
Yes |
Read address input to the memory. |
Input port WIDTHAD wide. |
wraddress[] |
Yes |
Write address input to the memory. |
Input port WIDTHAD wide. |
wren |
Yes |
Write enable input. |
|
inclock |
No |
Positive-edge-triggered clock. |
Used for registered write ports, for example, data, wraddress[], and wren. Can also be used for registered read ports, for example, rdaddress_a[], rdaddress_b[], rden_a, and rden_b. |
inclocken |
No |
Clock enable for inclock. |
|
rden_a |
Yes |
Read enable input. Disables reading when low (0). |
|
rden_b |
Yes |
Read enable input. Disables reading when low (0). |
|
outclock |
No |
Positive-edge-triggered clock. |
Used for the registered q_a[] or q_b[] port. Can also be used for registered read ports, for example, rdaddress_a[], rdaddress_b[], rden_a, and rden_b. |
outclocken |
No |
Clock enable for outclock. |
|
aclr |
Yes |
Asynchronous clear input. |
Affects registered inputs and outputs. |