TMC-20219: DSP Blocks with Restricted Fmax below Required Fmax
Description
Violations of this rule identify DSP blocks with restricted Fmax that prevents the circuit from meeting the required Fmax performance. This violation can occur when the DSP blocks are not fully registered and thus cannot achieve DSP posted maximum performance, or when the required Fmax exceeds a DSP Block's Fmax limit.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_pulse_width_slack | Reports a violation for timing endpoints that have a minimum-pulse-width slack below the value of this parameter. | double | 0.0 |
Recommendation
Add pipelines before and/or after the DSP block. Also make sure DSP packing rules are not violated to allow successful register-packing. Review Fitter Reports 'Fixed Point DSP Register Packing Details' and 'Floating Point DSP Block Details' for more details.
Refer to:
- DSP Block Performance Specifications for Intel Agilex Devices in the Intel Agilex®
Severity
Medium
Tags
| Tag | Description |
|---|---|
| dsp | Design rule checks related to DSP blocks inside the FPGA fabric. |
| minimum-pulse-width | Design rule checks related to minimum pulse width. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®