TMC-20213: Paths Failing Setup Analysis with Locally Routed Clock
Description
Violation of this rule identifies setup failing paths that use local routing resources in their clock path. As compared to local routing resources global resources have much less min max spread and consquently reduce the amount of clock skew.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
If there are no more available global resources, and you cannot reduce the number of clocks, reduce the number of fan-outs. Reducing fan-outs prevents the far routing that increases the skew present. Otherwise, promote the associated node on the clock path to global routing by specifying an assignment in the .qsf file "set_instance_assignment -name GLOBAL_SIGNAL <GLOBAL_CLOCK|GLOBAL|REGIONAL|ON|OFF> -to <instance_name>".
Note: Recommended value for GLOBAL_SIGNAL assignment is GLOBAL for Arria 10, Cyclone 10 families. Recommended value for GLOBAL_SIGNAL assignment is ON for any other familires.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| global-signal | Design rule checks related to global signals. |
| clock-skew | Design rule checks related to clock skew. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX