TMC-20100: Latch Loops Detected
Description
Violations of this rule identify loops consisting entirely of latches. There is no design restriction against such loops, but the loops may cause excessive time borrowing in the Timing Analyzer.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| depth | The maximum depth of a loop to search for before terminating. | integer | 10 | 0 | |
| filter | Only reports a violation for loops with latches that match this filter. | string | * |
Recommendation
If latch loops are not required, break them by placing a register between any two latches in each loop.
If latch loops are required, disable time borrowing for at least one latch in each loop with the following constraint: set_max_time_borrow
Severity
Low
Tags
| Tag | Description |
|---|---|
| latch | Design rule checks related to latches. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®