FLP-40005: Congested Routing Region
Description
High routing utilization, localized to a certain region, may lead to long routing detours having adverse impact on timing of critical nets in the region.
This condition is usually caused by one or more of the following sub-optimal floorplanning decisions:
- Smaller routing Logic Lock region for the associated logic partition or partial reconfiguration (PR) partitions.
- Incorrect placement of routing Logic Lock region.
- Sub-optimal shape of routing Logic Lock region.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| region_routing_threshold | (%) A violation is reported for routing regions that have routing congestion higher than specified in this parameter. | double | 70.0 | 100.0 | 0.0 |
Recommendation
Review whether the routing Logic Lock region is large enough to contain the associated logic, or if it must be moved or reshaped to follow connectivity of the interface logic.
Severity
Low
Tags
| Tag | Description |
|---|---|
| region-constraints | Design rule checks related to region constraints in the design (both placement and routing). |
Device Family
- Intel Agilex®
- Intel Agilex®
- Intel®Stratix® 10
- Intel®Arria® 10
- Intel®Cyclone® 10 GX