Plan Tab

Click the Plan tab to interactively place IP cores and other design elements in legal locations in the device periphery. The Plan tab displays a list of your project's design elements, alongside a graphical abstraction of the target device architecture.

You can assign design elements by dragging them from the Design Elements list and dropping them onto available device resources in the Chip or Package view. Alternatively, click the button next to any design element to display a list of legal locations. Single-click any legal location in the list to highlight the location in the floorplan. Double-click any legal location in the list to place in the floorplan. Interface Planner displays the approximate number of legal locations in the Legal Locations column. Clicking the button verifies the number of legal locations.

You can apply various filters to locate specific design elements or target device resources. Device resources are color coded by type, allowing quick access to any structure. Interface Planner accurately evaluates the constraints using the Fitter in real time. Select any physical design element and click Report Placeability of Selected Element to generate a report listing all legal placement options on the Reports tab. You can Export the contents of the report for analysis.

The Interface Planner Plan tab contains the following controls to help you place logic in the interface plan. Placement or unplacement in the interface plan does not apply to your Quartus Prime project until you add the generated Interface Planner constraints script to your project. Interface Planner is only available in Intel^® Quartus^® Prime Pro Edition software.

Table 1. Plan Tab Controls
Command	Description
	Lists legal locations for placement.
Locate Node	Display a list of Intel^® Quartus^® Prime Pro Edition tools where the selected design element is referrenced in the hierarchical database. If the Locate Node command is disabled for a specific element in the Design Elements list, it is because that element is not represented as an element in the design.
Autoplace All	Attempts to place all unplaced design elements in legal locations in the interface plan.
Autoplace Fixed	Attempts to place all unplaced design elements that have only one legal location into the interface plan.
Unplace All	Unplaces all placed design elements in the interface plan.
Right-click > Auto-place selected element	Attempts to place the selected design element and all its children in a legal location in the interface plan.
Chip View	Displays the target device chip. Zoom in to display chip details. For Intel Agilex^® 7 M-Series FPGAs only, this view also shows the placeable locations for hard memory NoC elements, including NoC initiators, targets, PLLs, and SSMs.
Package View	Displays the target device package. Zoom in to display chip details.
NoC View	For Intel Agilex^® 7 M-Series FPGAs only, this shows a filtered view of only the Network-on-Chip (NoC) initiators and targets in your design. NoC initiators and targets are visible as larger rectangles. The targets and initiators appear for both high-speed NoC along the top edge of the die, and the high-speed NoC along the bottom edge of the die. Initiators and targets that may share the same location in the Chip View are split into separate elements in the NoC View.
Show I/O Banks	Selects and color codes the I/O banks in the Plan tab.
Show Differential Pin Pair Connections	Displays a red connection line between a pair of differential pins. The Package View labels the positive and negative pins with the letters p and n, respectively.
Show PCIe Hard IP Interface Pins	Selects and color codes the PCIe Hard IP interface pins in the Plan tab. To access this command, right-click in the Plan tab package view, and select x1 Lanes, x2 Lanes. x4 Lanes, x8 Lanes, or by 16 Lanes. After enabling, view or change color coding in the Color Legend.
Show DQ/DQS Pins	Selects and color codes the PCIe Hard IP interface pins in the Plan tab. To access this command, right-click in the Plan tab package view, and select x4 Mode, x8/x9 Mode. x16/x16 Mode, or x32/x36 Mode. After enabling, view or change color coding in the Color Legend.
Right-click > Report Placeability of Selected Element	Displays detailed information on the Reports tab, showing legal locations in the interface plan for the selected cell in order of suitability for fitting.
Copy Current View	Copies the current interface plan to the clipboard for pasting into other files, such as word processing or presentation files.
Reset Plan	Unplaces all placed design elements and removes applied project assignments from the interface plan. Resets all project assignments to the enabled state. You must subsequently run Update Plan prior to placing design elements. This command only applies to your interface plan and does not impact your Intel^® Quartus^® Prime project assignments until you apply the Interface Planner script.
Load Floorplan	Allows you to select and load an Interface Planner Floorplan Format (.plan) file. You can save Interface Planner floorplan files in the format by clicking Save Floorplan.
Save Floorplan	Allows you to save your Interface Planner floorplan as a .plan file.
Undo/Redo buttons	The Undo button reverts the last change made in the Plan tab. Redo re-implements the last undo. Use these commands to step forward and backward though your plan changes.