TMC-20250: Paths Failing Setup Analysis within Platform Designer Interconnect

Description

The design contains failing timing path between Platform Designer interconnect components.

Name	Description	Type	Default Value
maximum_setup_slack	Reports a violation for timing paths that have a setup slack below the value of this parameter.	double	0.0
to_clock_filter	Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter.	string	*
minimum_number_of_adders	Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value.	integer	3
minimum_number_of_soft_mult_chains	Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value.	integer	2

Add pipeline stages between componentA and componentB by following these steps in Platform Designer:

Open the Platform Designer system that has this violation.
In the right-hand pane, go to Domains tab and click on Show System with Interconnect button, which launches the System with Platform Designer Interconnect window.
In the System with Platform Designer Interconnect window, go to Memory-Mapped Interconnect tab.
In the Interconnect drop-down menu, select the interconnect that has the failing path (for example, mm_interconnect_N in the following image).
Select the Show Pipelinable Locations check box. This results in displaying all pipelinable locations.
Identify components A and B in the interconnect, right-click on their gray boxes and select Pipelined.

Medium

Tag	Description
ip-parameterization	Design rule checks which look for parameterizable IP modules which may need to be adjusted to meet performance specifications.