ID:13455 Verilog HDL warning at <location>: expression attempts to divide or modulo by zero. Treated expression value as Don't Care (X) during synthesis.

CAUSE: An expression at the specified line in a Verilog Design File (.v) contains a divisor that is either a literal zero or an expression that reduces to zero. As a result, Quartus Prime Integrated Synthesis treated the expression value as Don't Care (X) during synthesis, which may result in a mismatch between the simulation and synthesis of the current design.

ACTION: To avoid simulation and synthesis mismatches, make sure the expression's divisor is not a literal zero or an expression that reduces to zero.