ID:17097 Verilog HDL warning at <location>: <string> was previously created using a AMS-enabled Verilog analyzer, since the current Verilog analyzer is not AMS-enabled, there is a high probability that a restore error will occur due to unknown AMS constructs

CAUSE: Quartus Prime Integrated Synthesis generated the specified warning message for the specified location in a Design File.

ACTION: No action is required. To remove the warning, address the issue identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this warning message.