ID:276028 Inferred ROM node "<name>" from synchronous logic. The ROM output initializes to GND and may not match the power-up state of your original design.

CAUSE: You described synchronous logic in a Verilog Design File (.v) or VHDL Design File (.vhd) that behaves as ROM. Analysis & Synthesis creates the specified ROM node to replace the synchronous logic. Later on, the ROM node infers an altsyncram megafunction that implements the functionality of the synchronous logic using the memory blocks in the target device. However, because you registered the read address and not the ROM output, the power-up state of the ROM may not match the power-up state of the original design. The ROM output always powers up to GND, but your design implies that the ROM output should power up to the value at address 0.

ACTION: No action is required unless you do not want Analysis & Synthesis to infer a ROM and/or change the functionality of your design. If you do not want an inferred ROM or if you want to preserve the functionality of your design, turn off the Auto ROM Replacement logic option. If you want the ROM but want to avoid receiving this message, replace the synchronous logic in your design with an explicit altsyncram megafunction.