ID:276030 ROM inference for design logic <text> using the altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=<number>, WIDTH_A=<number>) is disabled in formal verification mode

CAUSE: You turned on the Auto ROM Replacement logic option. You also specified a Formal Verification tool in the Tool Name box on the Formal Verification page of the EDA Settings page of the Settings dialog box. Analysis & Synthesis tried to infer an altsyncram megafunction with the specified OPERATION_MODE, NUMWORDS_A, and WIDTH_A parameter values from the specified logic in the current design. However, ROM inference using the altsyncram megafunction is not supported in formal verification mode. As a result, no ROM is created using the altsyncram megafunction.

ACTION: For Analysis & Synthesis to convert ROM logic into an altsyncram megafunction when compiling in formal verification mode, you have to treat the corresponding logic as a black box or instantiate the ROM using the corresponding megafunction. Note that if you treat the corresponding logic as a black box in an entity and the entity is parameterized, you need to create a wrapper entity that does not contain parameters. Otherwise, no action is required.