ID:171167 Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

CAUSE: Some Fitter assignments were invalid. These assignments can be created by the Quartus Prime software in the following scenarios:

• The design contains assignments that are no longer valid. Invalid assignments can occur when the source files change.
• The design was previously compiled with the Fitter netlist optimizations and then back-annotated. Back-annotation writes out location assignments for any nodes created by the Fitter netlist optimizations. However, there is no guarantee that the Fitter netlist optimizations will recreate the same nodes on this compilation. The recommended method to preserve the results of a compilation, with the Fitter netlist optimizations turned on, is to back-annotate locations and to use a Verilog Quartus Mapping File (.vqm) to save the netlist changes made by the Fitter.
• The design uses a Verilog Quartus Mapping File as a source that was generated from a previous compilation with register packing turned on and then back-annotated. Back-annotation writes out location assignments for both parts of a packing operation. Because the Verilog Quartus Mapping File represents the netlist after the packing operations have already been performed, one of the assignments may no longer apply.