ID:332102 Design is not fully constrained for <Setup or hold> requirements

CAUSE: The design is not fully constrained for the specified analysis type.

ACTION: Refer to the detailed Unconstrained Path Report (or report_ucp) to identify the unconstrained paths. Use the create_clocks or create_generated_clocks commands to constrain clocks. Use the set_input_delay and set_output_delay commands (or set_max_delay and set_min_delay to constrain I/O paths.